module pipeline_reg #(
  parameter WIDTH = 1,
  parameter RESET = 0
)(
  input clk,
  input rst,
  input we,
  input [WIDTH-1:0] d,
  output reg [WIDTH-1:0] q
);

always @(posedge clk) begin
  if (rst) begin
    q <= RESET;
  end else if (we) begin
    q <= d;
  end
end

endmodule
